Method for manufacturing semiconductor devices and plug

ABSTRACT

A method for manufacturing a semiconductor device is disclosed. The method is suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of an application Ser. No. 11/162,081,filed on Aug. 29, 2005, now allowed, which claims the priority benefitof Taiwan application serial no. 94104420, filed on Feb. 16, 2005. Theentirety of each of the above-mentioned patent applications is herebyincorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a fabrication method of asemiconductor device. More particularly, the present invention relatesto a fabrication method of a metal interconnect for a semiconductordevice.

2. Description of Related Art

The higher the level of integration for integrated circuits, the smallerthe semiconductor devices are being developed. Therefore, the size ofthe devices, for example, the width of the conducting line, the size ofthe gate, and the dimension of the plug shrinks to increase the level ofintegration. However, due to the miniaturizing of component devices, thedifficulties in the manufacturing process greatly increase, and thedemand for size precision also increases.

According to the conventional photolithography and etching processes, amisalignment often occurs during photolithography process in forming acontact window opening that exposes the source/drain region or a gate ora via that exposes the surface of an interconnect in the dielectriclayer of a memory device (ex: a flash memory) or an interconnect (ex: aconducting line), due to the increase of the level of integration andthe miniaturization of the device dimension. Furthermore, themisalignment during the photolithography process often leads to anexposure of other component devices neighbouring to the source/drainregion, the gate or the interconnect, designated to be exposed.

Turning to FIG. 1, FIG. 1 illustrates the cross sectional views of thecontact window openings for exposing a gate and a source region of theconventional trench flash memory. The conventional fabrication methodfor forming the contact window openings that respectively expose thedrain region and the gate region of the trench flash memory includesforming a trench gate structure 102 on a substrate 100, forming a gatedielectric layer 104 on the trench gate structure 102, forming a selectgate 106 on both a portion of the gate dielectric layer 104 which is atthe sides of the trench gate structure 102 and on the substrate 100,forming spacers 108 on the side walls of the select gate 106.Afterwards, in the substrate 100, a drain region 110 is formed at twosides of the trench gate structure 102 and the selected gate 106.Furthermore, a dielectric layer 112 is formed on the substrate 100, thena photolithography and etching process is performed to create contactwindow openings 114 and 116 in the dielectric layer 112. The contactwindow opening 114 exposes a portion of the drain region 110 and thecontact window opening 116 exposes a portion of the trench gate 102.

As expressed in the FIG. 1, while a misalignment or an inaccuratealignment occurs during a photolithography process, the contact windowopening 114 and 116 expose not only the assigned surfaces of the trenchgate structure and the drain region, but also a portion of neighbouringsurface 106 a next to the select gate 106. Therefore, while formingcontact plugs in the contact window 114 and the 116, the contact plugsare connected to the exposed select gate 106 through abnormal electricalconnection, leading to current leakage for the device, and abnormalelectrical performance.

SUMMARY OF THE INVENTION

Generally speaking, the present invention is directed to provide afabrication method for a semiconductor device, wherein the conductingdevice not intended to be electrically connected to the upper conductingstructure is relatively lower than the conducting device intended to beelectrically connected to the upper conducting structure. Therefore, anabnormal connection between the plug and the conducting device which isnot predetermined to form an electrical connection with the upperconducting structure can be prevented. Current leakage or abnormalelectrical performance can also be prevented.

In accordance to one aspect of the present invention, a fabricationmethod of a semiconductor device is provided. The method includesproviding a substrate, forming a first conducting structure and a firstdielectric layer on the first conducting structure, forming a secondconducting structure and a spacer at the side wall of the firstconducting structure covered by the first dielectric layer. The secondconducting structure is formed between the spacer and the firstconducting structure and between the spacer and the substrate.Thereafter, a portion of the second conducting structure is removed suchthat the upper surface of the second conducting structure is relativelylower than the upper surface of the first conducting structure tothereby form a first depression between the spacer and the firstconducting structure. A second depression is formed due to the secondconducting structure, which is disposed between the spacer and thesubstrate, being receded towards the side wall of the first conductingstructure. Afterwards, the second dielectric layer is formed on thesubstrate to fill in the first depression and the second depression.Furthermore, a via is formed in the second dielectric layer to exposethe upper surface of the first conducting structure. Finally, a plug isformed in the via.

According to the fabrication method of an embodiment in the presentinvention, the method for removing a portion of the second conductingstructure includes a wet etching process, and the etching solutionincludes a mixture of ammonia solution and hydrogen peroxide. Thecomposition ratio of the ammonia solution, hydrogen peroxide and waterin the etching solution ranges between 1˜5:1:100˜500. Besides, thetemperature of the ammonia-hydrogen peroxide solution is about 70˜90° C.Particularly, the etching selectivity of the material for the secondconducting structure is different from those of the first dielectriclayer and the spacer. The material of the second conducting structure isselected from the group consisting of polysilicon, silicide, andpolysilicon/silicon tungsten.

In accordance to another aspect of the present invention, a fabricationmethod of the via plug in the trench flash memory is provided, and thefabrication method is suitable for a substrate containing a trench typeflash memory. The trench type flash memory includes source/drain regionsin the substrate, a trench gate structure disposed in the substrate butprotruded from the surface of the substrate, a gate dielectric layercovering the trench gate structure, a select gate and a spacer on thetrench gate structure covered by the gate dielectric layer, wherein theselect gate is disposed between the spacer and the trench gate structureand between the spacer and the substrate. The fabrication methodincludes removing a portion of the select gate for the upper surface ofthe select gate to be relatively lower than the upper surface of thetrench gate structure to form a first depression between the spacer andthe first conducting structure. A second depression is formed due to thesecond conducting structure, which is disposed between the spacer andthe substrate, being receded towards the side wall of the firstconducting structure. Afterwards, the second dielectric layer is formedon the substrate to fill in the first depression and the seconddepression. Furthermore, in the dielectric layer, a first via and asecond via are formed, where the first via exposes the source/drainregions, and the second via exposes the upper surface of the trench gatestructure. Finally, a first via plug and a second via plug are formed inthe first via and the second via, respectively.

According to the fabrication method of the embodiment in the presentinvention, the method for removing a portion of the select gate includesa wet etching process, wherein the etching solution is includes amixture of ammonia solution and hydrogen peroxide. The composition ratioof the ammonia solution, hydrogen peroxide and water in the etchingsolution ranges between 1˜5:1:100˜500. Besides, the temperature of theammonia-hydrogen peroxide solution is about 70˜90° C. In particular, theetching selectivity of material for the select gate is different fromthose of the gate dielectric layer and the spacer. The material for theselect gate is selected from the group consisting of polysilicon,silicide, and polysilicon/silicon tungsten.

In accordance to yet another aspect of the present invention, afabrication method of a plug is provided, and the fabrication method issuitable for a substrate already formed with a first conductingstructure and a first dielectric layer, wherein the dielectric layercovers the first conducting structure. The fabrication method involvesin forming a second conducting structure at the side of the firstconducting structure and on the substrate, reducing the size of thesecond conducting structure for the upper surface of the secondconducting structure to be relatively lower than the upper surface ofthe first conducting structure, forming a second dielectric layer on thesubstrate to cover the first conducting structure and the secondconducting structure, forming a via in the second dielectric layer, andforming a via plug in the second dielectric layer.

According to an embodiment of the plug fabrication method of the presentinvention, the method for reducing the size of the second conductingstructure includes a wet etching process, wherein the etching solutionis formed with a mixture of ammonia solution and hydrogen peroxide. Theratio of the ammonia solution, hydrogen peroxide and water in theetching solution ranges between 1˜5:1:100˜500. Further, the temperatureof the ammonia-hydrogen peroxide solution is about 70˜90° C. Inparticular, the etching selectivity of the material for the secondconducting structure is different from those for the gate dielectriclayer and the spacer. The material for the second conducting structureis selected from the group consisting of polysilicon, silicide, andpolysilicon/silicon tungsten.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic cross sectional view of the conventional trenchtype flash memory device with a contact opening that exposes a gate anda contact opening that exposes a drain region.

FIG. 2A˜FIG. 2D are schematic cross sectional views according to anembodiment of the present invention showing the steps for fabricating aplug, where the plug is formed in the substrate and electricallyconnected to the component device of the trench type flash memory.

FIG. 3A˜FIG. 3D are schematic cross sectional views according to anembodiment of the present invention showing the steps for fabricating aplug, where the plug is formed in the dielectric layer and electricallyconnected to the lower layers of the conducting structure.

It is to be understood that the foregoing general description and thefollowing detailed description are exemplary and explanatory for theobjects, specification and merits of the present invention only, and arenot restrictive of the invention, as claimed.

DESCRIPTION OF THE EMBODIMENTS The First Embodiment

According to the present invention, the foregoing general descriptionand the following detailed description of an embodiment with referenceto the accompanying drawings are exemplary and explanatory for a plugfabrication of a trench type flash memory process. This invention,however, may be embodied in many different forms and should not beconstrued as limited to the embodiments set forth herein. The presentinvention is applicable to any process that is related to the formationof a plug in a dielectric layer, wherein the plug is electricallyconnected to an adjacent device underneath.

FIG. 2A to FIG. 2D are schematic cross sectional views showing the stepsfor fabricating a plug according to an embodiment of the presentinvention, wherein the plug is formed in the dielectric layer and iselectrically connected to the trench type flash memory.

Please referring to FIG. 2A, a substrate 300 that includes the trenchgate structure 302 is provided, wherein the trench gate structure 302can further include a tunnel oxide layer (not shown in the figures), afloating gate (not shown in the figures), a gate dielectric layer (notshown in the figures), and a control gate. Moreover, a gate dielectriclayer 304 is formed on the substrate 300 to cover the trench gatestructure 302, wherein the material for the gate dielectric layer 304is, for example, silicon oxide. Thereafter, a conducting layer 306 isformed on the gate dielectric layer 304, and selected from the groupconsisting of polysilicon and silicide; more preferable the material forthe conducting layer 306 is polysilicon/silicon tungsten. Afterwards, aninsulating layer (not shown in the figures) is formed on the conductinglayer 306, and a spacer 308 is formed at the side wall of the conductinglayer 306 by removing a portion of insulating layer. The material forthe spacer 308 is, for example, silicon nitride. It is noteworthy to bementioned that the etching ratio for the materials of the spacer 308 andthe gate dielectric layer 304, and the conducting layer aresignificantly different.

Please turning to FIG. 2B, after removing a portion of the conductinglayer 306 and a portion of the spacer 308, the upper part of the trenchgate structure 302 and a portion of the gate dielectric layer 304 on thesubstrate 300 are exposed, and a select gate 306 a and a spacer 308 aare formed. Accordingly, the select gate 306 a is disposed between thespacer 308 a and the trench gate structure 302, and between the spacer308 a and the substrate 300. Besides, the method for removing a portionof the conducting layer 306 and a portion of the spacer 308 includes anisotropic etching process.

Next turning to the FIG. 2C, an etching process is performed to remove aportion of the select gate 306 a; therefore, the select gate 306 b isrelatively lower than the spacer 308 a and the trench gate 302. At thesame time, the select gate 306 b disposed underneath the spacer 308 arecedes towards the side wall of the trench gate structure 302. In otherwords, the upper surface of the select gate 306 b is lower than theupper surface of the trench gate structure 302 to form a depression 307a between the spacer 308 a and the trench gate structure 302. Anotherdepression 307 b is formed due to the recession of the select gate 306 bdisposed between the spacer 308 a and the substrate 300 towards thetrench gate 302. Moreover, an etching process is performed by using anammonia-hydrogen peroxide solution to conduct a wet etching process andthe composition ratio of ammonia, hydrogen peroxide and water in theammonia-hydrogen peroxide solution ranges between 1˜5:1:100˜500,respectively the temperature for the ammonia-hydrogen peroxide solutionis preferably between 70˜90° C. It is noteworthy to be mentioned thatthe method for removing the portion of the select gate 306 a includes anetching process, and the etching selective ratio for the select gate 306b (same material for the conducting layer 306) is higher; therefore, aportion of the select gate 306 a can be selectively removed to form theselected gate 306 b without affecting the spacer 308 a and the exposedgate dielectric layer 304.

Continuing with the above description, a drain region 310 is formed inthe substrate 300 beside the two sides of the trench gate structure 302,the select gate 306 b and the spacer 308 a. Thereafter, a dielectriclayer 311 is formed on the substrate 300 filling the depression 307 aand the depression 307 b. The material for the dielectric layer 311 is,for example, silicon nitride. Furthermore, a dielectric layer 312 isformed on the dielectric layer 311.

Please referring to FIG. 2D, sequentially performing a planarizationprocess, a photolithography process and an etching process, contactwindow openings 314 and 326 are formed in the dielectric layer 312 and311, The surface of the drain region 310 is exposed by the contactwindow opening 314 and the surface of the trench gate 302 is exposed bythe contact window 316. Thereafter, the contact plugs 328 and 326 areformed in the contact window openings 314 and 316 to electricallyconnect to the trench gate structure 302 and the drain region 310,respectively.

In accordance to the embodiment of the present invention, the materialfor the gate dielectric layer 304 is, for example, silicon oxide; thematerial for the dielectric layer 311 is, for example, silicon nitride;the material for the dielectric layer 312 is, for example, siliconoxide. The fabrication processes for contact window 316 includesremoving a portion of the dielectric layer 312 using the dielectriclayer 311 as the etching stop layer and removing a portion of dielectriclayer 311 by applying the gate dielectric layer 304 as the etching stoplayer to, followed by removing a portion of the gate dielectric layer304 to expose the trench gate structure 302. In comparison with theneighbouring select gate 306 b and the trench gate structure 302, theselect gate 306 b is lower. Therefore, even if a misalignment occursduring the photolithography process, leading to a deviation of theposition of the contact window opening, the select gate 306 b which isadjacent to the trench gate structure 302 is still not being exposed bythe contact window opening 316 during the formation of the contactwindow opening 316 to expose the surface of the trench gate structure302.

In the similar manner, the select gate 306 b is receded towards thesidewall of the trench gate structure 302; therefore, even amisalignment occurs during the photolithography process leading adeviation of the position of the contact window opening, the select gate306 b which is adjacent to the drain region 310 is still not beingexposed by the contact window opening 314, during the formation of thecontact window 314 to expose the upper surface of the drain region 310.Afterwards, the plugs 326 and 328 which are formed in the contact windowopenings 314 and 316 will not contact the component devices that are notintended for (ex; the select gate 306 b of the embodiment) to resultwith an abnormal electrical contact. Therefore, the problems oftenoccurred in the prior art due to the higher level of the integration forthe device, such as, a misalignment during the photolithography processor an insufficient accuracy for the alignment, can be resolved toprevent a current leakage or an abnormal electrical performance due tothe unintentional electrical connection with the adjacent devices. Inaddition, the insulating ability between the select gate and the trenchgate structure can be improved.

According to the above embodiment, the fabrication method of the plug326 can be achieved through the self-alignment contact window process.

The Second Embodiment

According to the present invention, the foregoing general descriptionand the following detailed description of the embodiment with referenceto the accompanying drawings are exemplary and explanatory for thefabrication of plugs during the interconnect processing. This invention,however, may be embodied in many different forms and should not beconstrued as limited to the embodiments set forth herein. The presentinvention is applicable to any process that is related to the formationof a plug in a dielectric layer, wherein the plug is electricallyconnected to an adjacent device underneath.

FIG. 3A to FIG. 3D are schematic cross sectional views showing the stepsof fabrication of a plug fabrication in an interconnect manufacturingprocess according to another embodiment of the present invention,wherein the plug is formed in the dielectric layer and is electricallyconnected to the conducting structure at the lower level.

Please referring FIG. 3A, a substrate 400 including a conductingstructure 402 is provided. A dielectric layer 404 is formed on thesubstrate 400 to cover the conducting structure 420, and the materialfor the dielectric layer 404 is, for example, silicon oxide. Thereafter,a conducting layer 406 is formed on the gate dielectric layer 404 andthe material for the conducting layer 406 is selected from the groupconsisting of polysilicon and silicide. More preferable the material forthe conducting layer 406 is formed with polysilicon/silicon tungsten.Afterwards, an insulating layer (not shown in the figures) is formed onthe conducting layer 406, and a spacer 408 is formed at the side wall ofthe conducting layer 406 by removing a portion of insulating layer. Thematerial for the spacer 408 is, for example, silicon nitride. It isnoteworthy to be mentioned that the etching ratio for the materials ofthe spacer 408 and the dielectric layer 404, and the conducting layerare significantly different.

Please turning to FIG. 3B, after removing a portion of the conductinglayer 406 and a portion of the spacer 408, an upper part of theconducting structure 420 and a portion of the dielectric layer 404 onthe substrate 400 are exposed. A conducting structure 406 a and a spacer408 a are thereby formed. Therefore, the conducting structure 406 a isdisposed between the spacer 408 a and the conducting structure 420, andbetween the spacer 408 a and the substrate 400. Besides, the method forremoving the portion of the conducting layer 406 and the portion of thespacer 408 includes an anisotropic etching process.

Next turning to the FIG. 3C, an etching process is performed to remove aportion of the conducting structure 406 a to form the conductingstructure 406 b that is relatively lower than the spacer 408 a and theconducting structure 420. At the same time, the conducting structure 406b disposed underneath the spacer 408 a is receded towards the side wallof the conducting structure 420. In other words, the upper surface ofthe conducting structure 406 b is lower than the upper surface of theconducting structure 420 to form a depression 407 a between the spacer408 a and the conducting structure 420. Another depression 407 b isformed due to the recession of the conducting structure 406 b betweenthe spacer 408 a and the substrate 400 towards the conducting structure420. Moreover, an etching process includes a wet etching process usingan ammonia-hydrogen peroxide solution, and the composition ratio ofammonia, hydrogen peroxide and water in the ammonia-hydrogen peroxidesolution ranges between 15:1:100˜500. The temperature of theammonia-hydrogen peroxide solution ranges between 70˜90° C.; morepreferable at the temperature of 85° C. It is noteworthy to be mentionedthat the method for removing the portion of the conducting structure 406a is an etching process, and the etching selective ratio for theconducting structure 406 b (same material for the conducting layer 406)is higher; therefore, the portion of the conducting structure 406 a canbe selectively removed to form the conducting structure 406 b withoutaffecting the spacer 408 a and the exposed dielectric layer 404.

Continuing with the above description, a dielectric layer 411 is formedon the substrate 400 to fill the depression 407 a and the depression 407b. The material for the dielectric layer 411 is, for example, siliconnitride. Furthermore, a dielectric layer 412 is formed on the dielectriclayer 411.

Please referring to FIG. 3D, an opening 424 is formed in the dielectriclayer 412 and 411, and the opening 424 exposes the surface of theconducting structure 420. Thereafter, the plug 426 is formed in theopening 424; and the plug 426 is electrically connected to theconducting structure 420.

In accordance to the embodiment of the present invention, the materialfor the dielectric layer 404 is, for example, silicon oxide; thematerial for the dielectric layer 411 is, for example, silicon nitride;the material for the dielectric layer 412 is, for example, siliconoxide. The fabrication processes for opening 424 is by using thedielectric layer 411 as the etching stop layer to remove a portion ofthe dielectric layer 412, applying the dielectric layer 404 as theetching stop layer to remove a portion of dielectric layer 411, andremoving a portion of the dielectric layer 404 to expose the conductingstructure 420. Regarding the neighbouring conducting structures 406 band 420, the conducting structure 406 b is lower. Therefore, even if amisalignment occurred during a photolithography process leading to adeviation of the position of the contact window opening, the conductingstructure 406 b which is adjacent to the conducting structure 420 isstill not being exposed by the opening 424. Accordingly, the plug 426subsequently formed in the opening 424 will not electrically contact thecomponent device that are not intended for (ex; the conducting gate 406b in the embodiment) to result with an abnormal electrical contact.

In conclusion of the above description, the present invention at leastprovides the following advantages.

(1) According to the plug fabrication method in a trench type flashmemory manufacturing process of the present invention, by using thesignificant differences of the etching selective ratio between thematerials for the select gate, spacer and the gate dielectric layer, aportion of select gate is removed to have the select gate lower than thetrench gate structure. Further, the select gate is receded towards theside wall of the trench gate structure. Therefore, even a misalignmentor insufficient alignment accuracy occurred during the photolithographyprocess, and the position of the contact window is formed deviated, thecomponent device which is not intended for electrical connection, willnot be exposed. Furthermore, the current leakage or abnormal electricalperformance due to the unintended electrical connection can beprevented. In addition, the insulating ability between the select gateand the trench gate structure can be improved.

(2) According to the plug fabrication method in a trench type flashmemory manufacturing process of the present invention, by usingmaterials that have significant differences in the etching selectiveratios for the conducting structure, the dielectric layer and thespacer, a portion of conducting structure is removed to have theconducting structure lower than the conducting structure which ispre-determined to be electrically connected. Further, the conductingstructure is receded towards the side wall of the conducting structurewhich is predetermined to be electrically connected. Therefore, even amisalignment or insufficient alignment accuracy occurred during thephotolithography process, and the position of the contact window isformed deviated, the component device which is not intended forelectrical connection will not be exposed. Furthermore, a currentleakage or abnormal electrical performance due to the unintentionalelectrical connection can be prevented.

(3) The plug fabrication of the present invention, by using materialsthat have significant differences in the etching selective ratios forthe conducting material and the dielectric layer, the conducting devicenot intended to be electrically connected to the upper layer of theconducting structure is lower than the conducting device which ispredetermined to be electrically connected to the upper layer of theconducting structure. Therefore, when a via or a contact window openingis formed in the dielectric layer, the conducting device, which is notintended to be electrically connected to the upper layer of theconducting structure but is neighbored to the conducting devicepredetermined to be electrically connected to the upper layer of theconducting structure, will not be exposed. Furthermore, the unintendedelectrical connection between the plug subsequently formed and theconducting device not predetermined to be electrically connected to theupper layer of the conducting structure can be prevented. A currentleakage or an abnormal electrical performance can be obviated.

It will be apparent that the above mentioned description with attachedfigures are exemplary and explanatory for the objects, specification andmerits of the present invention only, and are not restrictive of theinvention, those skilled in the art that various modifications andvariations can be made to the present invention without departing fromthe scope or spirit of the invention. In view of the foregoing, it isintended that the present invention cover modifications and variationsof this invention provided they fall within the scope of the followingclaims and their equivalents.

What is claimed is:
 1. A fabrication method of a semiconductor device,comprising: forming a first conducting structure on a substrate; forminga first dielectric layer on the first conducting structure; forming asecond conducting structure on the first conducting structure covered bythe first dielectric layer and on the substrate; forming a spacer at twosides of the first conducting structure and on the second conductingstructure; removing a portion of the second conducting structure for anupper surface of the second conducting structure to be lower than anupper surface of the first conducting structure to form a firstdepression between the spacer and the first conducting structure and forthe second conducting structure which is disposed between the spacer andthe substrate to recede toward the side wall of the first conductingstructure to form a second depression; forming a second dielectric layerto cover the second conducting structure and fill the first depressionand the second depression; and forming a plug in the second dielectriclayer.
 2. The fabrication method of a semiconductor device as recited inclaim 1, wherein the step of removing a portion of the second conductingstructure comprises performing an isotropic etching process.
 3. Thefabrication method of a semiconductor device as recited in claim 2,wherein the isotropic etching process further comprises of an etchingsolution, and the etching solution comprises an ammonia-hydrogenperoxide solution.
 4. The fabrication method of a semiconductor deviceas recited in claim 3, wherein a composition ratio for ammonia, hydrogenperoxide and water in the ammonia-hydrogen peroxide solution rangesbetween 1˜5:1:100˜500.
 5. The fabrication method of a semiconductordevice as recited in claim 3, wherein a temperature for theammonia-hydrogen peroxide solution ranges between 70˜90° C.
 6. Thefabrication method of a semiconductor device as recited in claim 1,wherein a material for the second conducting structure is selected fromthe group consisting of polysilicon, silicide, and polysilicon/silicontungsten.
 7. A fabrication method for a plug, which is applicable to asubstrate already comprising a first conducting structure and a firstdielectric layer thereon, and the first dielectric layer covering thefirst conducting structure; the fabrication method comprising: forming asecond conducting structure on the substrate beside a side of the firstconducting structure; reducing a size of the second conducting structurefor an upper surface of the second conducting structure to be lower thanan upper surface of the first conducting structure; forming a seconddielectric layer on the substrate, wherein the second dielectric layercovers the first conducting structure and the second conductingstructure; forming a via in the second dielectric layer; and forming avia plug in the via.
 8. The fabrication method for the plug as recitedin claim 7, wherein the step of reducing the second conducting structurecomprises a wet etching process.
 9. The fabrication method for the plugas recited in claim 8, wherein an etching solution for the wet etchingprocess comprises an ammonia-hydrogen peroxide.
 10. The fabricationmethod for the plug as recited in claim 9, wherein a composition ratioof ammonia, hydrogen peroxide and water in the ammonia-hydrogen peroxidesolution ranges between 1˜5:1:100˜500.
 11. The fabrication method forthe plug as recited in claim 9, wherein a temperature of theammonia-hydrogen peroxide solution ranges between 70˜90° C.
 12. Thefabrication method of a semiconductor device as recited in claim 7,wherein the via exposes the upper surface of the first conductingstructure.